A closer look at Arm A-profile support for non-maskable interrupts
A long-standing limitation of the Arm A-profile architecture has been the lack of support for non-maskable interrupts (NMIs). However, as announced in Arm A-Profile Architecture Developments 2021 Arm is adding support in both the CPU and Generic Interrupt Controller (GIC) architecture for NMIs. But what exactly is an NMI, how does operating systems software use these features, and why are they called non-maskable when there are several ways to mask them? This blog post explores these questions in more detail.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Blogs
- Taking a closer look at the Rambus GDDR6 PHY IP Core
- Functional, Fast, and Ultra-Low Power: A Live Look at Weebit's Second IP Module
- A look at the PowerVR graphics architecture: Tile-based rendering
- Delivering a Better Support Experience for IP Customers
Latest Blogs
- ReRAM in Automotive SoCs: When Every Nanosecond Counts
- AndeSentry – Andes’ Security Platform
- Formally verifying AVX2 rejection sampling for ML-KEM
- Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2
- Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform