A closer look at Arm A-profile support for non-maskable interrupts
A long-standing limitation of the Arm A-profile architecture has been the lack of support for non-maskable interrupts (NMIs). However, as announced in Arm A-Profile Architecture Developments 2021 Arm is adding support in both the CPU and Generic Interrupt Controller (GIC) architecture for NMIs. But what exactly is an NMI, how does operating systems software use these features, and why are they called non-maskable when there are several ways to mask them? This blog post explores these questions in more detail.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related Blogs
- Taking a closer look at the Rambus GDDR6 PHY IP Core
- Functional, Fast, and Ultra-Low Power: A Live Look at Weebit's Second IP Module
- A look at the PowerVR graphics architecture: Tile-based rendering
- Delivering a Better Support Experience for IP Customers
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility