Symmetric Encryption IP

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Compare 172 Symmetric Encryption IP from 44 vendors (1 - 10)
  • SM4 Cipher Engine
    • The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
    • Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
    Block Diagram -- SM4 Cipher Engine
  • SNOW-V Stream Cipher Engine
    • The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems.
    • It conforms to the official SNOW-V mechanism, published in 2019 by the IACR Transactions on Symmetric Cryptology, as an extensive revision of SNOW 3G stream cipher.
    Block Diagram -- SNOW-V Stream Cipher Engine
  • P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
    • Small size: From 70K ASIC gates (at throughput of 18.2 bits per clock)
    • 500 MHz frequency in 90 nm process
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
  • AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
    • The High-Performance AES IP core is a fast, silicon-proven cryptographic engine designed for systems with demanding encryption workloads.
    • Built on a 20 S-box parallel architecture, it delivers exceptional AES-128/256 encryption and decryption throughput while supporting standard modes including ECB, CBC, and CTR (excluding GCM, XTS, and CBC-MAC).
    Block Diagram -- AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
  • AES-XTS Multi-Booster
    • The AES-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suitable for a wide range of low-cost & high-end applications (including key, tweak, input and output registers and Galois field multiplier).
    Block Diagram -- AES-XTS Multi-Booster
  • AES Mutli-Purpose crypto engine
    • The AES Multi-Purpose crypto engine includes a generic and scalable implementation of the AES algorithm and a configurable wrapper making the solution suitable for a wide range of low-cost & high-end applications.
    Block Diagram -- AES Mutli-Purpose crypto engine
  • 3DES Crypto Engine
    • The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Information Processing Standards Publication (FIPS 46-3) of the National Institute of Standards and Technology (NIST).
    Block Diagram -- 3DES Crypto Engine
  • KASUMI Crypto Engine
    • The KASUMI IP core is 3GPP confidentiality and integrity algorithms (UEA1/UIA1) stream cipher for telecommunication applications, requiring high performance with reduced silicon resources.
    • It is optimized for maximum throughput and minimum latency.
    Block Diagram -- KASUMI Crypto Engine
  • SNOW3G Crypto Engine
    • ASIC and FPGA
    • ETSI specifications compliant
    • Supports:
    • Data interface: AMBA (AXI/AHB) with optional DMA
    Block Diagram -- SNOW3G Crypto Engine
  • ARIA Crypto Engine
    • The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea.
    • It is compliant with the RFC 6209 specification and can support several cipher modes including authenticated encryption.
    Block Diagram -- ARIA Crypto Engine
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