Symmetric Encryption IP

Compare 165 Symmetric Encryption IP from 45 vendors (1 - 10)

Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
SM4-GCM Multi-Booster crypto engine
- ASIC & FPGA
- High throughput
- Guaranteed performance with small packets
SM4 Encoder and Decoder
- Compliant with GBT.32907-2016
- Support both encryption and decryption
- Support ECB, CBC and multiple ciphering modes
SM4 Cipher Engine
- The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
- Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
Advanced DPA- and FIA-resistant AES SW library
- Ultra-strong side-channel and SIFA protection at high performance
- NIST FIPS-197 compliant
- AES-128/192/256 encryption and decryption
- Tunable protection level
DPA- and FIA-Resistant Balanced FortiCrypt AES IP Core
- A wide range of configurations to match the user’s cost/performance target
- Low latency
- Passes the rigorous Test Vector Leakage Assessment (TVLA) methodology at 1B traces
- Protected against fault injection attacks, including SIFA
- Tunable protection level
- Optional embedded internal PRNG for random masking
DPA and FIA-Resistant Ultra-Compact FortiCrypt AES IP core
- Ultra-compact
- Ultra-efficient in terms of performance per gate
- Passes the rigorous Test Vector Leakage Assessment (TVLA) methodology at 1B traces
- Protected against fault injection attacks, including SIFA
- Tunable protection level
DPA- and FIA-resistant Ultra Low Power FortiCrypt AES IP core
- Ultra-low power in terms of performance per watt
- Passes the rigorous Test Vector Leakage Assessment (TVLA) methodology at 1B traces
- Protected against fault injection attacks, including SIFA
- Tunable protection level
- Optional embedded internal PRNG for random masking
DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
- Ultra-high bandwidth due to multi-pipeline architecture, HUNDREDs Gbps (@500 MHz on a 45nm tech. process)
- GCM authentication tag protection (patent pending)
- Ultra-strong side-channel attack protection (at least 1B traces)
- Protected against fault injection attacks including SIFA
AES Engine IP
- The AES engine IP is a high-performance cryptographic engine operates in AES NIST Federal information processing standard FIPS-197.
- It supports AES-ECB AES-XTS mode and 128/256 key-length both encryption/decryption.
- The core engine supports 128/256/512 data width operation.