Hash and HMAC Accelerator IP

Compare 84 Hash and HMAC Accelerator IP from 36 vendors (1 - 10)

SHA-3 Crypto Core
- SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach.
- The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard.
- A common core is available for diverse ASIC & FPGA applications.
SHA-3 Crypto Engine
- FIPS 202 and FOS 180-4 compliant
- SHA3-224, SHA3-256, SHA3-384, SHA3-512
- SHAKE-128, SHAKE-256
Hash-based post-quantum hardware accelerator
- Power side-channel secure (SCA) Keccak engine
- AXI4-Lite (64-bit 1x subordinate)
- NIST FIPS-202 SHA3-224/256/384/512
SHA-256 IP
- SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles.
- Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz.
SHA512 & SHA384 core
- Simple register based interface
- 81 clock cycles per 1024 bits of input data
- AMBA 3 APB slave interface
- DMA flow-control interface
SHA3 core for accelerating NIST FIPS 202 Secure Hash Algorithm
- Supports variable length SHA-3 Hash Functions
- Supports Extendable Output Functions (XOF)
- Configurable architecture for achieving the required performance and silicon area
SHA256 & SHA224 core
- Simple register based interface
- 65 clock cycles per 512 bits of input data
- AMBA 3 APB slave interface
- DMA flow-control interface
SHA1 core
- Simple register based interface
- 82 clock cycles per 512 bits of input data
- AMBA 3 APB slave interface
- DMA flow-control interface
SHA-256 Secure Hash Function
- Compliant to FIPS 180-2 specification of SHA-256.
- Bit padding internally implemented.
- Supports 2^64-1 bits maximum message length.
- Supports input message length multiple of 8-bit.
- Initial value of the chaining variables selected before synthesis.
SHA-1 Secure Hash Function
- Compliant to FIPS 180-1 specification of SHA-1.
- Bit padding internally implemented.
- Supports 2^64-1 bits maximum message length.
- Supports input message length multiple of 8-bit.