Hash and HMAC Accelerator IP

Compare 81 Hash and HMAC Accelerator IP from 38 vendors (1 - 10)

SHA-1 Processor
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- Xilinx and Altera netlist available for various devices.
MD5 Processor
- RFC 1321 compliant.
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
SHA-256 Processor
- This core is a fully compliant implementation of the Message Digest Algorithm SHA-2⁵⁶. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
- The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.
Fast Hash IP core
Tiny Hash IP core
- The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate applications.
- The core is available in versions which support any combination of the secure hashing algorithms described in the Secure Hash Standard, FIPS PUB 180-3; namely SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512.
- It can also support the standard Hash-based Message Authentication Code (HMAC) algorithm described in FIPS PUB 198-1 which is widely used for data authentication and integrity checking in a number of common data security protocols.
SHA3 IP Core
- SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard specifies methods for generating secure hash values using the SHA-3 algorithm.
- SHA3 IP Cores support the SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256 functions, and are byte-oriented in their implementation.
SHA-3 Crypto Core
- SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach.
- The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard.
- A common core is available for diverse ASIC & FPGA applications.
SHA-3 Crypto Engine
- FIPS 202 and FOS 180-4 compliant
- SHA3-224, SHA3-256, SHA3-384, SHA3-512
- SHAKE-128, SHAKE-256
Hash-based post-quantum hardware accelerator
- Power side-channel secure (SCA) Keccak engine
- AXI4-Lite (64-bit 1x subordinate)
- NIST FIPS-202 SHA3-224/256/384/512
SHA-256 IP
- SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles.
- Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz.