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Public Key Accelerator IP

Public key cryptography, or asymmetric cryptography, uses mathematical functions to create codes that are exceptionally difficult to crack, enabling designers to protect sensitive data and systems. Common public key algorithms include RSA, Digital Signature Algorithm (DSA), and Diffie-Hellman (DH), which require the calculation of complex modular exponentiation operations to encrypt, decrypt, sign, and verify data used in data encryption, digital signatures, and key exchanges. Similarly, the Elliptic Curve Cryptography (ECC) based algorithms require complex mathematical operations, such as point multiplications, and are designed to support devices with limited computing power or memory to encrypt internet traffic.

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Compare 69 Public Key Accelerator IP from 18 vendors (1 - 10)
  • ECC7 Elliptic Curve Processor for Prime NIST Curves
    • Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part of the “Suite B” of cryptographic algorithms approved by the NSA.
    • The design is fully synchronous, with the exception of the seed part, and available in both source and netlist form.
    • The core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
    Block Diagram -- ECC7 Elliptic Curve Processor for Prime NIST Curves
  • RSA2-AHB Accelerator Core with AHB Interface
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the AHB interface.
    Block Diagram -- RSA2-AHB Accelerator Core with AHB Interface
  • Scalable RSA and Elliptic Curve Accelerator
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the interface.
    Block Diagram -- Scalable RSA and Elliptic Curve Accelerator
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
  • NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
    • Minimal Resource Requirements
    • Secure Architecture
    • FIPS 186-4 and SP 800-56A compliant
    Block Diagram -- NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
  • Modular Exponentiation Core
    • Fully synthesisable RTL source code
    • VHDL/Verilog testbench with test vectors
    • User documentation
    Block Diagram -- Modular Exponentiation Core
  • Falcon IP Core
    • Falcon IP Core is a post-quantum digital signature algorithm (DSA).
    • It is currently under development. It is going to be compliant with Falcon specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    • Additionally, Falcon IP Core will be enhanced to achieve compliance with NIST Falcon Standart when it is released. 
    Block Diagram -- Falcon IP Core
  • Dilithium IP Core
    • Dilithium IP Core is a post-quantum digital signature algorithm (DSA).
    • It currently supports Sign and Verify functions, with key generation functionality planned for future implementation.
    • This IP is compliant with Dilithium specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    Block Diagram -- Dilithium IP Core
  • KYBER IP Core
    • supports encapsulation and decapsulation operations
    • supports all modes K=2,3,4.
    • is compliant with Kyber specification round 3.
    • has fully stallable input and output interfaces. 
    • Key generation feature is going to be implemented in the near future.
    Block Diagram -- KYBER IP Core
  • RSA Keygen IP Core
    • RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'.
    • This standard specifies methods for generating RSA key pairs.
    • RSA Keygen IP Cores support key pair generation up to 4096 bits.
    Block Diagram -- RSA Keygen IP Core
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