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LPDDR5 IP

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Search (106)
Compare 106 LPDDR5 IP from 17 vendors (1 - 10)
  • LPDDR6/5X/5 Controller IP
    • Supports JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
    • Support for data rates up to 14.4 Gbps for LPDDR6, 10.67 Gbps for LPDDR5X, and 6.4 Gbps for LPDDR5
    • Multiport Arm® AMBA® interface AXI™4 with managed QoS or single-port host interface to the DDR controller
    • DFI 5.2 compliant interface to Synopsys LPDDR6/5X/5 PHY
    Block Diagram -- LPDDR6/5X/5 Controller IP
  • LPDDR5X/5/4X/4 PHY & Controller
    • The  LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller.
    • It is fully compliant with the JEDEC standard. Optimized for low-power and high-speed applications, it ensures robust timing and a small silicon area.
    • The PHY IP contains specialized functions to guarantee high-performance I/Os, critical timing, low power and jitter with programmable fine-grain control for any SDRAM interface.
    Block Diagram -- LPDDR5X/5/4X/4 PHY & Controller
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
  • LPDDR5X/5/4X/4 PHY for 16nm
    • Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 PHY for 16nm
  • LPDDR5/4x/4 combo PHY on 14nm, 12nm
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5/4x/4 combo PHY on 14nm, 12nm
  • LPDDR5/4x/4 PHY IP for Samsung 14LPU
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5/4x/4 PHY IP for Samsung 14LPU
  • Memory Controller
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- Memory Controller
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
    • Look-ahead activate, precharge, and auto-precharge logic
    • Parity protection for all stored control registers
    • PHY interface based on DFI 5.1 standard
    Block Diagram -- LPDDR5T / LPDDR5X / LPDDR5 Controller
  • LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
    • LPDDR5 Verification IP (VIP) is a tool designed to simulate and validate the functionality of LPDDR5 memory controllers. It ensures compliance with LPDDR5 specifications, covering high-speed data transfer, power management, error detection, and system integration.
    • LPDDR5 VIP is essential across various industries, enabling high-performance systems to function optimally. It is utilized in mobile devices, automotive systems, high-performance computing, AI/ML, and more, ensuring efficient memory interfaces in diverse applications
    Block Diagram -- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
  • LPDDR4/4x/5/5x PHY
    • Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
    • Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
    • Support for 16, 32 and 64-bit operation
    Block Diagram -- LPDDR4/4x/5/5x PHY
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