LPDDR5T / LPDDR5X / LPDDR5 Controller

Overview

Key Features

• Support for all LPDDR5T/5X/5 devices
• Bank management logic monitors status of each bank
• Queue-based user interface with reordering scheduler
• Look-ahead activate, precharge, and auto-precharge logic
• Parity protection for all stored control registers
• PHY interface based on DFI 5.1 standard
• Each controller instance supports a single channel
• Multiple rank support (typically 2 or 4)
• Supports WCK:CK ratio 4:1
• Supports x16 mode
• Burst length BL16 and BL32
• Data bus inversion (DBI) feature (read and/or write)
• Supports masked write (MWR)
• Mode register write (MRW) and mode register read (MRR) functions
• Background ZQ calibration mode and command-based ZQ calibration mode
• Supports LPDDR5 speeds up to 9.6 Gbps/pin
• Supports all defined LPDDR5 channel densities (up to and including 32Gb, including non-binary densities)
• LPDDR5 bank architecture BG mode and 16B mode
• LPDDR5 per-bank refresh and all-bank refresh
• LPDDR5 refresh management
• LPDDR5 device self-refresh mode
• LPDDR5 device power-down mode
• Automatic generation of initialization and refresh sequences
• Built-in activity monitor
• Optional multi-burst capability
• Full set of add-on cores available
• Can be delivered fully integrated and verified with target LPDDR PHY
• Customization and integration services available

Applications

• Mobile, Automotive, IoT, Laptop PCs, Edge

Deliverables

• Core (source code)
• Testbench (source code)
• Complete documentation
• Complete documentation
• Maintenance updates

Technical Specifications