OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.
The LPDDR5X/5/4X/4 Combo OPHY features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables LPDDR5/4 Combo OPHY to overcome issues with long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interruption of data traffic. The programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between OMC and the LPDDR5X/5/4X/4 DRAM without sacrificing performance.
The LPDDR5X/5/4X/4 Combo OPHY was designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage.
At the system level, the LPDDR54 Combo OPHY was designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications and application processors.
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
Overview
Key Features
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
- Multiple frequency states
- DQ Vref training supported
- PHY independent training and DRAM initialization
- Firmware (FW) based training
- Proprietary microcontroller with custom ISA
- Multiple DFICLK: CK ratios and DFICLK:CK: WCK ratio
- Tx and Rx channel equalization
- Voltage and temperature tracking of timing and impedance control circuit
- Flexible floor planning/bump mapping
- Transmitter and Receiver channel equalization
- Multiple low power saving states with IO retention
Benefits
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
- Voltage and temperature drift compensation to maintain optimal data eye
- Firmware-based PHY independent initialization of DRAM and training
- Multiple frequencies state FSP with a fast switching time
- Multiple voltage domains for optimal voltage vs. frequency tuning
- Support low-cost package substrate and PCB
Block Diagram
Applications
- Consumer edge devices
- Digital set-top-boxes
- TVs
- SSD controllers
- Application processors
Deliverables
- Hard & Soft IP
- GDSII, LEF, LVS, timing models, etc.
- Verilog behavior models and encrypted RTL
- Synthesis and STA constraints
- Example test benches
- Documentation
- PHY Technical Reference Manual
- Implementation, package, and PCB design guidelines
- Test and characterization guidelines
- Physical verification reports
Technical Specifications
Foundry, Node
5nm
Maturity
Silicon-proven
Availability
Now
Samsung
Pre-Silicon:
5nm
Silicon Proven: 5nm
Silicon Proven: 5nm