LPDDR5X/5/4X/4 PHY & Controller
The LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller.
Overview
The LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power and high-speed applications, it ensures robust timing and a small silicon area. The PHY IP contains specialized functions to guarantee high-performance I/Os, critical timing, low power and jitter with programmable fine-grain control for any SDRAM interface.
Key features
- Rates from 200 Mbps to
- 10.7 Gbps (LPDDR5X)
- 6400 Mbps (LPDDR5)
- 4266 Mbps (LPDDR4X/4)
- Compliant with JESD209-5 (LPDDR5X/5) and JESD209-4 (LPDDR4X/4)
- x16/x32/x64 data bus width extendable
- Supports LPDDR4X 0.6 V IO voltage and LPDDR5 0.5 V/0.3 V IO voltage
- Supports LPDDR5 WCK mode, Data copy, Write X and Link ECC features
- Independent read and write timing adjustments with auto calibration
- Programmable write post-amble (0.5 tCK or 1.5 tCK)
- Supports both PoP and discrete memory package
- Supports various low power modes, supports DFS and retention modes
- Supports point to point memory sub-systems and multi-rank
- PVT compensation and timing calibration for all corner reliability
- At speed BIST, scan insertion, PAD and internal loopback modes
- Various power-down modes for low power including self-refresh support
- Low jitter with superior noise rejection
- APB Port register access interface
- Supports both wire-bond and flip-chip packaging
- Wire-bond speed is package limited
Block Diagram
Benefits
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Extensive EDA tool support for various design and automation flow
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing
What’s Included?
- Extensive documentation
- Models
- LIB
- LEF
- Place-and-route abstracts
- LVS netlist
- GDSII files
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about DDR IP core
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Frequently asked questions about DDR Controller IP cores
What is LPDDR5X/5/4X/4 PHY & Controller?
LPDDR5X/5/4X/4 PHY & Controller is a DDR IP core from Innosilicon Technology Ltd listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.