How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
OPENEDGES Technology, Inc.
Category:
DDR
Memory Controller
Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduli…
Overview
Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduling algorithm and high-speed implementation. Designed to address the needs of next-generation SoCs, the OMC saves a significant amount of area and power while supporting the highest levels of the DRAM bandwidth.
| DDR Type | Target Applications |
| GDDR6 | HPC (Al/ML), Edge PC, Data Center, Server, PC, Coin |
| LPDDR4 | Mobile, Automotive, loT, Broadcasting |
| LPDDR4X/3 Controller | Mobile, Automotive, loT, Surveillance, STB, DTV, SSD |
| LPDDR5X/5/4X Controller | Automotive, HPC (Al/ML), Broadcasting |
| DDR4/3 Controller | STB, DTV, SSD, Network, Surveillance |
| HBM3 Controller | HPC (Al/ML), Coin, Data Center |
Key features
- DRAM Support
- JEDEC compliant LPDDR5x/5/4x/4/3, DDR4/3, GDDR6, HBM3 support
- Up to 4 ranks/channel (configurable)
- High Performance
- A proprietary out-of-order scheduling algorithm
- Dual-PHY control for 2x DRAM channel bandwidth with a single OMC instance
- Low Power Consumption
- Ultra-low power consumption with HW-controlled dynamic DRAM frequency scaling
- Automatically handles training activities required for frequency change
- Automated DRAM power management
- Special Features
- BFE (Bus Front End) for multi-master ports (optional)
- Configurable Options
- DRAM types (LPDDR5x/5, DDR4, LPDDR4x/4, DDR3/LPDDR3, GDDR6)
- Channel DQ width (x16, x32, x64)
- Number of AXI master ports (up to 8)
- AXI master data width and frequency
- Request queue depth
- Write and read data queue depth
Block Diagram
OMC block diagram
Benefits
- Intensive DRAM Utilization
- Over 90% DRAM utilization using a proprietary out-of-order scheduling algorithm
- Optimal pipeline architecture
- Ultra-Low Power Consumption
- Hardware-controlled dynamic DRAM frequency scaling
- Automates training activities required for frequent changes
- Highly area-efficient
- Extremely Low Latency
- Low latency even in high utilization scenarios
- Suppression of peak latency using the latency-aware algorithms
- Safety & Security
- Inline ECC
- Security Firewall
Applications
- Automotive
- Application Processors
- HPC/Super Computing
- Block Chain/Crypto Currency
- Digital TV
- Data Center
- Game Console
- Entertainment
- Graphic Cards
What’s Included?
- OMC is packaged with the following items for all eligible companies:
- IP core RTL
- Standalone Simulation Environment
- Management SW
- IP Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
OMC
Vendor
OPENEDGES Technology, Inc.
Provider
OPENEDGES Technology, Inc.
HQ:
Korea
OPENEDGES is an IP technology provider for Smart Computing enabling Internet of Smart Things. OPENEDGES delivers IPs in two key technology areas in Smart Computing; 1) Artificial Intelligence (Deep Learning) Accelerator and 2) Memory Subsystem IP.
For Memory Subsystem, we provide Memory Controller IP (OMC), LPDDR5x/5/4 PHY & High speed Network on-chip interconnect IP (OIC). OPENEDGES is the only IP company providing DDR controller, DDR PHY IP & High speed NoC bus interconnect IP all together. When used together within an SoC, OMC, OPHY and OIC provide significant synergy of higher performance, reduced SoC design efforts and a lot easier post-silicon debugging/tuning. And our Artificial Intelligence Accelerator (ENLIGHT) features higher compute density & low-power consumption through our unique bit-precision optimization technology.
ENLIGHT and our Memory system IP gives synergy of high efficiency for performance demanding Artificial Intelligence acceleration task. Our IPs are silicon proven and market proven with many Tier 1 semiconductor companies.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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Frequently asked questions about DDR Controller IP cores
What is Memory Controller?
Memory Controller is a DDR IP core from OPENEDGES Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.