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Memory & Libraries IP for TSMC

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Compare 67 Memory & Libraries IP for TSMC from 12 vendors (1 - 10)
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  • 16nm
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
    • AD_SLVS_LVDS is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is flexible enough for any system.
    • To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm.
    • This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.
    Block Diagram -- 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
  • 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
    • This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
    • The high-voltage GPIO is a flip-chip compatible 1.8V to 3.3V GPIO design, compliant with multiple I/O standards.
    • It comes as a macro cell with a pair of I/Os in each cell, allowing differential I/O interface capabilities as well.
    Block Diagram -- 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
  • 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
    • This library is a production-quality, silicon-proven I/O Library in TSMC 16nm technology.
    • The High Performance GPIO is a flip-chip compatible, 1.2V to 1.8V GPIO design, compliant with multiple high-speed Single-Ended and Differential I/O standards.
    • The macro cell comes as a pair of I/Os that can be configured as a differential I/O or two independent single- ended I/Os.
    Block Diagram -- 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
  • SLVS Transceiver in TSMC 28nm
    • This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process.
    • Designed with 1.8V thick oxide devices and a standard low-voltage core interface at 0.8V, this transceiver ensures robust operation across a wide temperature range (-40°C to 125°C).
    • Supporting high-speed differential signaling up to 2Gbps, it delivers ex- ceptional signal integrity with low jitter and precise eye diagrams.
    Block Diagram -- SLVS Transceiver in TSMC 28nm
  • 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
    • A TSMC 28nm HPM/HPC/HPC+ Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, 5V I2C ODIO, 1.8V & 3.3V Analog Cells, ESD and more.
    • A key attribute of this silicon-proven library is to detect and adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    • The GPIO can be configured as input, output, open-source, or open-drain with an optional 60kohm pull-up or pull-down resistor.
    Block Diagram -- 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
  • LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
    • The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
  • eTCAM (Embedded Ternary Content Addressable Memory IP
    • One cycle operation latency (without priority encoder)
    • Valid Bit per entry to reduce power
    • Valid Bit reset in one cycle support
    • Mask input option for bit-write and masked search key
    Block Diagram -- eTCAM (Embedded Ternary Content Addressable Memory IP
  • IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
    • Certus offers dedicated 1.8V, 3.3V and switchable 1.8V/3.3V General-Purpose IO (GPIO) solutions.
    • GPIO features include:
    • I2C / SMBUS Open-Drain I/O features include:
    • LVDS I/O features include:
    Block Diagram -- IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
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