LDPC IP

Irregular parity check matrix
Layered decoding
Minimum sum algorithm
Soft decision decoding
BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12

The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.

The CMS0035 DVB-Satellite Modulator is an integrated core featuring our DVB-S/-DSNG modulator (CMS0010) and DVB-S2/-S2X modulator (CMS0025) cores. The CMS0035 core provides all the functionality required to address the requirements of the ETSI forward-link satellite Standards EN 300 421 (DVB-S), EN 301 210 (DSNG), EN 302 307-1 (DVB-S2) and EN 302 307-2 (DVB S2X), with additional support for DVB-S2X VLSNR operation
The core can operate in a constant coding-and-modulation (CCM) mode for all Standards and in the enhanced variable-coding-and modulation (VCM) and adaptive-coding-and modulation (ACM) modes provided by DVB-S2 and DVB-S2X.

The CMS0025 DVB-S2/S2X Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the ETSI DVB-S2 forward-link satellite standard (EN 302 307), section-1 together with the section-2 extensions (DVB-S2X), with additional support for DVB-S2X VLSNR operation. The core can operate in CCM and VCM/ACM modes.
The core provides all the necessary processing steps to modulate a single transport stream (or baseband frame) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels
The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.
LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
Intel's 5G Low-Density Parity Check (LDPC) Intel FPGA Intellectual Property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification.

Soft-Decision Demapper, Derandomizer, Deinterleaver, Depuncturer, and LDPC Decoder are included
Support for 4k and 8K FFT sizes
Support for 16-QAM modulation