Very Low Latency BCH Codec

These cores implement a Bose-Chaudhuri-Hocquenghem (BCH) error correction code configured to process a k-bit codeword, providing the capability to correct up to t bit errors per block. On the decoder side, more than t errors will be typically detected with “uncorrectable” cff pin asserted.

The core targets the high-performance very-low-latency error correction ASIC applications with high k (about 500) and small t (3-5) using Bose–Chaudhuri–Hocquenghem codes (BCH codes) that prioritize latency over size. The performance of the BCH10 core is 1 word (k bits) per clock (that is, new codeword is produced or accepted on every clock). The clock rates of 2-3 GHz and more are possible in high-speed semiconductor technology nodes.

The latency of the encoder core is 2 clocks. The decoder latency is 5-7 clocks input-to-output data.

• High performance, low latency
• Small size (75K gates for k=298, t=4) configuration, the core uses just 17K gates in ASIC)
• Entirely self-contained (no external RAM required)
• Data inputs and outputs have flip-flops attached to the pins

• Synthesizable Verilog RTL source code
• Test bench (self-checking)
• Test vectors
• Expected results
• Software Development Kit (SDK)
• User Documentation