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BCH IP

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Search (21)
Compare 21 BCH IP from 6 vendors (1 - 10)
  • DVB-S2-LDPC-BCH IP
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
    Block Diagram -- DVB-S2-LDPC-BCH IP
  • Block Diagram -- BCH Encoder and Decoder IP Core
  • BCH Decoder IP
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    Block Diagram -- BCH Decoder IP
  • DVB-S2X Wideband BCH and LDPC Decoder
    • Compliant with DVB-S2 and DVB-S2X
    • Support for decoding of BBFRAMEs
    • Support for ACM, CCM, and VCM
    Block Diagram -- DVB-S2X Wideband BCH and LDPC Decoder
  • BCH Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    • Area and power optimized implementation.
    Block Diagram -- BCH Decoder
  • 512B/ECC16 Nand Flash BCH Encoder/Decoder
    • 2-16 bit error correction
    • 2-900 data bytes per block
    • Low-latency, synchronous design
    • Pipelined correction operation supports 3 concurrent corrections
  • DVB-C2 Receiver (including LDPC and BCH decoder)
    • Compliant with ETSI 302 769 (DVB-C2).
    • Support for short blocks (16200 bits) and long blocks (64800 Bits).
    • Support for all modulation schemes (16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM).
    • Support for all interleaving schemes of all modulation schemes.
  • DVB-S2 BCH and LDPC Encoder and Decoder
    • Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
    • Support for short blocks (16200 bits) and long blocks (64800 bits).
    • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
    • Support for all interleaving schemes of all modulation schemes.
  • 1KB/ECC96 NAND Flash BCH Encoder/Decoder
    • 2-96 bit error correction
    • 2-1800 data bytes per block
    • Low-latency, synchronous interface
    • Optional asynchronous ECC mode for faster correction computations
  • ISDB-S3-LDPC-BCH Decoder IP
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
    • BCH decoder works on GF (2^16 ) and corrects up to t =12 errors
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Semiconductor IP