The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.
If configured for ACM operation, the FEC mode can dynamically change on a frame-by-frame basis. The design has been optimised to provide excellent performance in FPGA devices.
A description of the processing steps follows:
- Soft Decision Generator. This block calculates the Log Likelihood Ratios (LLRs) for individual bits encoded in the complex IQ symbols received from the demodulator.
- De-Interleaver. Reverses the block-interleave and writes LLR data into the LDPC input buffer. LDPC Decoder. Performs LDPC decoding of both the main payload data and also the TMCC Header. The decoder uses a modified min-sum algorithm for optimum performance end efficient resource usage. BCH Decoder. Error-checks the LDPC output and corrects small numbers of residual LDPC errors. Provides reliable detection of uncorrectable decoding errors which are then flagged in the output stream. De-Scrambling. Reverses the energy dispersal randomisation using the DVB-S2 scrambling polynomial.
- TS Rate Adaption. The Decoder output can be optionally configured to produce a constant-rate TS whose byte-rate tracks the off-air symbol rate. Register Bank. The register bank provides a simple 32-bit interface for reading status registers within the decoder block. Full details of the registers are contained in the IP Users Guide.
