IP Catalog > Analog IP > ADC / DAC IP > A/D Converter (ADC) IP

A/D Converter (ADC) IP

An ADC IP (Analogue to Digital Converter) is a data converter which allows digital designs to interface with the real world by encoding an analogue signal into a binary code.

The primary function of an A/D Converter semiconductor IP is to enable seamless interaction between analog input sources and digital processing units. High-quality A/D Converters ensure accurate data capture and conversion, minimizing loss of information during the transformation process. As the demand for more precise and faster data processing increases, the importance of these IPs grows, driving innovations in resolution, sampling rates, and power efficiency.

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Compare 521 A/D Converter (ADC) IP from 63 vendors (1 - 10)
  • 12-bit ADC on Samsung 8nm LN08LPP
    • The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports conversion rate (FS) up to 1MS/s, designed in 8nm CMOS FinFET process.
    • It consists of a 16-to-1 analog input MUX, a successive approximation (SAR) type monolithic ADC, a clock generator, and level-shifters for low voltage digital interface.
    Block Diagram -- 12-bit ADC on Samsung 8nm LN08LPP
  • 12-bit ADC on Samsung 4nm LN04LPE
    • ADC0401X is a 1.2-V/0.75-V dual supply voltage 16-channel 12-bit Analog-to-Digital Converter (ADC) that supports conversion rate (FS) up to 1 MS/s, designed in 4-nm CMOS FinFET process.
    Block Diagram -- 12-bit ADC on Samsung 4nm LN04LPE
  • 11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
    • The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
    • It is a hybrid-SAR ADC, with 11-bit resolution and a sampling rate of 5 gigasamples-per-second (GSPS).
    Block Diagram -- 11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
  • Pipeline ADC
    • High Sampling Rate: Capable of sampling up to 125 million samples per second, suitable for high-speed applications
    • 8-bit Resolution: Provides 8-bit digital output, delivering precise quantization of input signals
    • Pipeline Architecture: Ensures low latency and high throughput, ideal for real-time processing
    • Low Power Consumption: Optimized for minimal power usage, enhancing energy efficiency in portable and battery-powered devices
    Block Diagram -- Pipeline ADC
  • Sigma-Delta ADC
    • Dynamic Range: 100 dB
    • Resolution: High-resolution digital output
    • Sigma-Delta Modulation: Advanced noise shaping and low distortion
    • Power Consumption: Optimized for low power, typically in the milliwatt range
    Block Diagram -- Sigma-Delta ADC
  • SAR ADC
    • High Sampling Rate: Capable of sampling up to 640 million samples per second, making it suitable for ultra-high-speed applications
    • 12-bit Resolution: Delivers 12-bit digital output, providing superior precision and accuracy in signal quantization
    • SAR Architecture: Ensures high speed and low latency with excellent power efficiency
    • Ultra-Low Power Consumption: Optimized for minimal power usage, ideal for energy-sensitive applications
    Block Diagram -- SAR ADC
  • 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
    • Rail-to-Rail IQ ADC Input Capability
    • 65dB IQ ADC SNR
    • Programmable Full-Scale IQ DAC Output Current
    • 65dB IQ DAC SNR
    Block Diagram -- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
  • 180nm 13-bit Sigma-Delta ADC
    • 1.8V low-power 32MHz single-bit switched-capacitor SD Modulator-based 7.8125kHz-to-62.5kHz-Nyquist-rate ADC with programmable Decimation Rate
    Block Diagram -- 180nm 13-bit Sigma-Delta ADC
  • 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
    • Integrated Dual-Channel Continuous-time Delta-Sigma Modulator (I + Q)
    • Integrated Dual decimate-by-8 Cascaded-Integrator-Comb Decimation Filter
    Block Diagram -- 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
  • 12-bit 40nm 1.1V 80MHz Asynchronous-SAR IQ ADC
    • Rail-to-Rail Input Capability
    • Dual (I and Q) Channels
    • Scalable Power Consumption
    • No need for external high-speed SAR clock
    Block Diagram -- 12-bit 40nm 1.1V 80MHz Asynchronous-SAR IQ ADC
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