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A/D Converter (ADC) IP

An ADC IP (Analogue to Digital Converter) is a data converter which allows digital designs to interface with the real world by encoding an analogue signal into a binary code.

The primary function of an A/D Converter semiconductor IP is to enable seamless interaction between analog input sources and digital processing units. High-quality A/D Converters ensure accurate data capture and conversion, minimizing loss of information during the transformation process. As the demand for more precise and faster data processing increases, the importance of these IPs grows, driving innovations in resolution, sampling rates, and power efficiency.

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Search (497)
Compare 497 A/D Converter (ADC) IP from 65 vendors (1 - 10)
  • 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
    • The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
    • It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.
    Block Diagram -- 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
  • 12 Bit 20 MS/s Pipeline ADC on XFAB XH035
    • This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half the sampling rate needs to be applied.
    • This ADC is built as a single-ended architecture and is designed to convert input signals from 0.5 – 2.3V at 3.3V supply voltage with up to 10 MHz input bandwidth with 12 bits resolution.
    Block Diagram -- 12 Bit 20 MS/s Pipeline ADC on XFAB XH035
  • 16 Bit 10 kS/s Incremental Delta-Sigma ADC on AMS H35
    • This fully differential ADC is designed to convert full swing (-1V to +1 V) input signals as well as unipolar input signals (0V to + 1V), each with 16 bits resolution.
    • Low-frequency noise reduction is provided using chopper-modulation.
    • The embedded power down mode provides a linear relation between power consumption and conversion rate of the ADC.
    Block Diagram -- 16 Bit 10 kS/s Incremental Delta-Sigma ADC on AMS H35
  • Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018
    • The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
    • The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s) and power consumption down to 1.9 µW. The input voltage range is quasi-rail-to-rail guaranteeing more than + 1.7 V@ 1.8V power supply.
    • An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.
    Block Diagram -- Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018
  • 15 Bit 192 kS/s Sigma-Delta ADC on XFAB XH018
    • The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ratio.
    • It is built using typical second order architecture using correlated-double-sampling method. The target application is sampling of transient input voltages with 8k S/s with low-power and 192 kS/s respectively.
    Block Diagram -- 15 Bit 192 kS/s Sigma-Delta ADC on XFAB XH018
  • 15 Bit 8 kS/s Sigma-Delta ADC on XFAB XH018
    • Resolution: 15 bit
    • Conversion rate: 8 kSps
    • Power consumption: 1.3 mW @ 1.8V
    Block Diagram -- 15 Bit 8 kS/s Sigma-Delta ADC on XFAB XH018
  • 12 Bit 40 MS/s Pipeline ADC on XFAB XH018
    • Resolution: 12 bit
    • Conversion rate: 4 - 40 MS/s
    • Power consumption: 95 mW @ 1.8 V
    Block Diagram -- 12 Bit 40 MS/s Pipeline ADC on XFAB XH018
  • 12 Bit 54 kS/s Cyclic ADC on XFAB XH018
    • This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution for sampling frequencies up to 54 kS/s for continuous input signals.
    • This single ended ADC is designed to convert input signals with input swing of 1.9 V. The resolution is configurable (12 bit, 16 bit). Reference voltages can be generated on-chip or applied from outside.
    Block Diagram -- 12 Bit 54 kS/s Cyclic ADC on XFAB XH018
  • 12 Bit 17 kS/s Cyclic ADC on XFAB XH018
    • This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution for sampling frequencies up to 17 kS/s for continuous input signals.
    • This single ended ADC is designed to convert input signals with input swing of 1.9 V. The resolution is configurable (12 bit, 16 bit). Reference voltages can be generated on-chip or applied from outside.
    Block Diagram -- 12 Bit 17 kS/s Cyclic ADC on XFAB XH018
  • 16 Bit 13 kS/s Cyclic ADC on XFAB XH018
    • Resolution: 16 bit
    • Conversion rate: up to 13 kS/s
    • Power consumption: 50 uW @ 2.4 V
    Block Diagram -- 16 Bit 13 kS/s Cyclic ADC on XFAB XH018
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