Verification challenges of embedded memory devices

Ramon Acosta, Nascentric
(08/14/2006 9:00 AM EDT), EE Times
 
In 1981 an industry leader was rumored to have said, "Nobody will ever need more than 640KB of RAM." Whether he said it or not might be up for debate, but it soon became abundantly clear that 640K would be never enough.

Amazingly, even after 25 years we aren't sure that memory requirements can be bound. Gigabyte memories, once the realm of science fiction, are taken for granted. Every new generation of consumer electronic gadget has applications that bedazzle the senses, greedily devouring more memory in the process. One can watch the latest video on a cell phone, take a picture with a pen and get the latest weather info on a wristwatch. Try doing that with 640KB of RAM!

As we push towards greater integration, current system-on-chip (SOC) designs dramatically increase memory content and show no signs of relenting. According to the Semiconductor Industry Association (SIA), memory already dominates over 60% of silicon area in SOC designs, and is projected to represent over 90% of the die area by end of the decade. New SOC designs are beginning to take on the appearance of a memory-chip with logic surrounding it.

The predominance of memory in SOC designs is made more acute by the variety of memory types that are being used today. The multi-functional nature of current designs is reflected by the International Technology Roadmap for Semiconductors (ITRS). Having an SOC design embedded with a DRAM along with a CAM, an EPROM, and a multi-port SRAM is not uncommon.

There can be several instances of the same memory that might exist on the chip with different architectures for high-performance, low-power, other form-factors, and so on. These variations require that, for design and analysis purposes, multiple instances of the same memory be treated as distinct entities.

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