Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets
By Doug Daniels, Rambus
EEWeb, (January 23, 2019)
There are a number of key changes to DDR that introduce new design challenges. However, savvy designers will use the transition time to nail down solutions.
Server and system designers are gearing up to transition from DDR4 to DDR5 server dual-inline memory module (DIMM) buffer chipsets in their upcoming designs. A foremost consideration involves major specification changes. It is expected that designers will focus on the top (most significant) half-dozen of these changes to advance server designs.
Those are the data and clock rate, VDD (or operating voltage), power architecture, channel architecture, burst length, and improvements for higher-capacity DRAM support. These new changes present special design considerations covered in the second part of this article.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Transitioning from C/C++ to SystemC in high-level design
- Migrating your embedded PCB design from DDR2/3 to DDR4 SDRAMs
- From ADAS to Autonomous Cars: Key Design Lessons
- Analog IP to protect SoC from side-channel attacks
Latest Articles
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation