The "BIST" Thing That Happened to SoC Design
Not so long ago, in a design galaxy that now seems far, far away, RTL designers did not have to worry about a testable integrated circuit (IC). "Leave that to the test guys," they would say, and it was so.
However, as chip complexity increased and designers turned to complex system-on-chip (SoC) designs, test was taking more and more time and test engineers were complaining that the designers were creating virtually untestable designs. Test costs were going out of control as the cost of test was rivaling the cost of manufacturing a chip.
"There has to be a better way," the test engineers complained. And sure enough, there was a better way, with embedded test. By designing testability into the chip design in the first place, RTL designers can significantly reduce the cost of test.
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related White Papers
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- How to manage changing IP in an evolving SoC design
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- How to Elevate RRAM and MRAM Design Experience to the Next Level
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design