The "BIST" Thing That Happened to SoC Design
by Philip George and James Fujimoto
Not so long ago, in a design galaxy that now seems far, far away, RTL designers did not have to worry about a testable integrated circuit (IC). "Leave that to the test guys," they would say, and it was so.
However, as chip complexity increased and designers turned to complex system-on-chip (SoC) designs, test was taking more and more time and test engineers were complaining that the designers were creating virtually untestable designs. Test costs were going out of control as the cost of test was rivaling the cost of manufacturing a chip.
"There has to be a better way," the test engineers complained. And sure enough, there was a better way, with embedded test. By designing testability into the chip design in the first place, RTL designers can significantly reduce the cost of test.
Not so long ago, in a design galaxy that now seems far, far away, RTL designers did not have to worry about a testable integrated circuit (IC). "Leave that to the test guys," they would say, and it was so.
However, as chip complexity increased and designers turned to complex system-on-chip (SoC) designs, test was taking more and more time and test engineers were complaining that the designers were creating virtually untestable designs. Test costs were going out of control as the cost of test was rivaling the cost of manufacturing a chip.
"There has to be a better way," the test engineers complained. And sure enough, there was a better way, with embedded test. By designing testability into the chip design in the first place, RTL designers can significantly reduce the cost of test.
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related White Papers
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- How to manage changing IP in an evolving SoC design
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- How to Elevate RRAM and MRAM Design Experience to the Next Level
Latest White Papers
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant
- Attack on a PUF-based Secure Binary Neural Network
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics