It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
By Michael White, David Abercrombie, and John Ferguson (Siemens EDA)
EETimes (July 18, 2023)
“Shift left for Architects…”
“What is shift left security?…”
“Adopting a shift left culture…”
Search the term “shift left” and you’ll see dozens of articles discussing the definition of shift left, how shift left can improve operations and results in a variety of industries, or even why shift left doesn’t work. Clearly it’s a topic of much discussion, and many companies are actively working towards implementing shift left principles and practices…or so they think. But a successful shift left strategy contains many components—ignoring even one of them reduces the chance of achieving the gains you’re expecting to see.
Larry Smith, a software engineer, is credited with coining the phrase “shift left” back in 2001, in an article focusing on improving the flow between software development and quality assurance testing1. He asserted that, to improve the overall software development process, teams needed to develop test cases earlier, perform testing earlier, and automate testing as much as possible. His conclusion, “Bugs are cheap when caught young,” encapsulates the concept and value of the shift left approach.
To read the full article, click here
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related Articles
- Get More Reliable Automotive ICs with a Shift Left Design Approach
- Reliability challenges in 3D IC semiconductor design
- Shift Left for More Efficient Block Design and Chip Integration
- Larger IC makers won't shift to foundries, concludes research firm
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability