How to manage changing IP in an evolving SoC design
By Ryan Chen, ArterisIP
EDN (September 23, 2022)
In a previous article, Getting started in structured assembly in complex SoC designs, an unexceptional system-on-chip (SoC) design was shown to contain hundreds of intellectual property (IP) blocks. Also, it was demonstrated how connections between these IP blocks may involve hundreds or thousands of ports with multiple tie-off options.
Some IP blocks may come from third-party suppliers, while others are developed internally. The problem is that any of these blocks may experience revision changes throughout the course of design. This is especially true of internally developed IP, which may undergo multiple revisions due to evolving specifications and requirements. Managing these changes as the design evolves can quickly become a nightmare.
Why do things change?
The ancient Greek philosopher Heraclitus of Ephesus (535-475 BC) famously noted: “The only constant in life is change.” When it comes to the IP blocks forming an SoC, the goal is to make the process of change as easy as possible.
In the case of IP from third-party vendors, changes during a particular project are relatively rare. One exception is when the design team detects and reports a bug or other issue, and the vendor responds by generating a new revision of the IP to address the problem. Another scenario is when it becomes necessary to replace an IP from one vendor with an equivalent IP from another vendor, which—among other things—may necessitate changes at the interface.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Low Power Design in SoC Using Arm IP
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks