SoC realization: Finally the "Killer App" that will allow EDA to grow again?
Ajoy K. Bose PhD, Chairman, President and CEO, Atrenta
EETimes (5/11/2011 4:46 AM EDT)
There has always been much hand-wringing in the electronic design automation (EDA) business about growth. We look at the markets we serve – semiconductors and electronics – and see enticing upward-bound curves as electronics permeate more of our everyday lives. We discuss and debate how EDA should participate more fully in that trajectory, painfully aware of our single-digit growth rates. We constantly ask ourselves how EDA can participate more fully in the value chain that it enables. We search for our own version of the killer app, the iPad of EDA, that will finally ignite a dramatic take-off in sales.
It’s unlikely to happen, at least in a global and disruptive way like the iPad. Despite the never-ending need for innovation to deal with IC complexity, historically EDA has always been a replacement business serving a relatively finite market of users. When you have automation as part of your segment definition, we should expect that customers will only pay at best a small premium to what they can actually do themselves. We sell new tools that replace old tools to pretty much the same group of users. This has been predictable in the EDA classic perspective because the tool business has been tied tightly to Moore’s Law of shrinking geometries and increasing complexity. Evergreen, but a replacement business. These factors inherently limit the industry’s growth and prevent the emergence of any kind of consumer-driven home-run product.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- Can Hardware-Assisted Verification Save SoC Realization Time?
- Fast, Thorough Verification of Multiprocessor SoC Cache Coherency
- Techniques for CDC Verification of an SoC
- Moore's Law is Dead: Long Live SoC Designers
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events