Can Hardware-Assisted Verification Save SoC Realization Time?
Srivatsan Raghavan, Senior Architect, Vayavya Labs
EETimes (11/8/2013 10:00 AM EST)
I recently attended Cadence-Live in Bangalore to learn about the latest and greatest in verification technologies. As expected, many of the sessions were geared towards System-on-Chip (SoC) verification using formal and simulation techniques. The main draw was the hardware-assisted (HA) verification session track. Yes, I use the word "hardware-assisted" since the word "emulation" is overloaded, confusing, and a misnomer.
It looks as if the "Big Three" EDA vendors are gearing up for the next battle to capture the SoC verification market. Hardware boxes such as Palladium have been around for years. So, why the sudden buzz? My take? Two factors as follows
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- Hardware-assisted verification gate counts soar
- Surveying the hardware-assisted verification landscape
- Verification challenges of ADC subsystem integration within an SoC
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems