Prevention, quality and other innovations in hardware debug
Neil Johnson, XtremeEDA Corp
EETimes (7/2/2012 12:08 PM EDT)
Debug represents a major cost to hardware development organizations and a constant source of frustration for engineers. According to a survey commissioned by Mentor Graphics in 2010, verification engineers spend an estimated 32% of their time debugging code[1]. In a typical 8-hour day, that translates to more than 2.5 hours specifically dedicated to fixing defects.
Spending 2.5 hours debugging code can make for a frustrating day for an engineer, but what does that mean for the organization? According to the EE Times Global Salary and Opinion Survey from 2010, the annual compensation for a North American engineer, including bonuses and overtime pay, averaged $107,300[2]. From that, it’s easy to make a best case, back-of-the-napkin estimate capturing the cost of employing a medium sized team of engineers to build a reasonably sized ASIC. The result is a very big number.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
- A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
- How NoCs ace power management and functional safety in SoCs
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design