eFPGAs Bring a 10X Advantage in Power and Cost
By Flex Logix Technologies
eFPGA LUTs will out ship FPGA LUTs by the end of the century because of the advantages of reconfigurable logic being built into the chip: cost reduction, lower power and improved performance.
Many systems use FPGAs because they are more efficient than processors for parallel processing and can be programmed with application specific co-processors or accelerators typically found in datacenters, wireless base stations and enterprise storage.
The need for improved processing in the cloud is driven by faster search results which drives revenue. FPGAs provide very valuable programmability in these systems but customers would like to find a way to reduce the power and size to increase compute density. The way to achieve this is to integrate the FPGA into the companion SoC.
Why? Because it saves power and cost by as much as 10X. The 10X in cost reduction does not even include the saving from inventory reduction and testing when there is an extra chip on the board. For example, integrating the FPGA can reduce costs from $300 down to 20$ of additional silicon cost and the power similarly.
To read the full article, click here
Related Semiconductor IP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
- eFPGA on GlobalFoundries GF12LP
- eFPGA Hard IP Generator
- Radiation-Hardened eFPGA
Related Articles
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks