Using platform independent models to proliferate code across multiple application environments
By Irv Badr, Telelogic/IBM
Embedded.com (09/08/09, 11:46:00 PM EDT)
Software for embedded systems has not only to work properly, it must also meet tight memory, processor, and storage constraints of a target platform. The application has to be properly architected from the start to meet the platform's physical and timing constraints, even when the RTOS, processor, memory, and I/O can change several times during the life of a product.
Model-based design makes it possible to develop source code for multiple compilers, languages, and underlying platforms, even different Real-Time Operating Systems, all from a common design.
By capturing the intended application's architecture in a high level Platform Independent Model (PIM), the resulting application source code becomes a truly sharable entity, not just across the same application, but many different ones on other platforms.
PIM generates sharable components and raises the level of abstraction for an application: developers can directly execute a model without needing RTOS integration or writing lengthy programs.
They can validate applications very early in the development cycle, fixing errors at the design level, instead of through source code inspection and debugging. The proven model is deployed as an embedded application on any given platform, with the modelling tool used to define platform specificity.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- Using a Versatile, Independent IP Platform for SoC Design
- Creating Virtual Platform using The OCP-IP Modeling kit
- Pondering the SoC platform
- Panel finds many ways to build a platform
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval