Network-on-chip (NoC) interconnect topologies explained
By Andy Nightingale, ArterisIP (July 26, 2023)
Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.
Functional IP blocks connect to the network-on-chip (NoC) via sockets. In the case of an initiator IP, the socket serializes and packetizes the data generated by the IP, assigns an ID to the packet, and dispatches it into the network. When the packet arrives at its destination IP, the associated socket extracts the data from the packet and transforms it into the protocol required by the IP. A large number of packets can be in flight throughout the network at any given time.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- NoC Verification IP
- Smart Network-on-Chip (NoC) IP
- NoC System IP
- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
Related Articles
- An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)
- Performance Verification Methods Developed for an HDTV SoC Integrating a Mixed Circuit-Switched / NoC Interconnect (STBus/VSTNoC)
- Interconnect (NoC) verification in SoC design
- NoC Interconnect Fabric IP Improves SoC Power, Performance and Area
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks