Interconnect (NoC) verification in SoC design

Ramneek Real (Toshiba), Janak Patel & Bhavin Patel (eInfochips)
EDN (February 27, 2015)

Within the increasing complexity of SoC design, bus-interconnect is a key component which has led to evolution in the design of interconnect with a new socket-based approach. The socket is defined as: the decoupling of IP core and interconnect functionality. The socket-based approach provides interconnect IP to reuse without rework and it provides a bus-independent interface. This allows on-chip interconnect to provide application-specific features. The socket also isolates the cores from the internal switching logic and provides the following advantages:

• IP core decoupling with protocol conversion
• Command translation
• Clock domain crossing
• Width conversion
• Security management features for protecting a specific memory region from different cores (i.e., protecting Instruction Fetch area from Write commands)
• Configuration-based error handling support

To read the full article, click here