Meeting signal integrity requirements in FPGAs with high-end memory interfaces
Programmable Logic DesignLine
Wider parallel data buses, increasing data rates, and multiple loads are challenges for high-end memory interface designers. The demand for higher bandwidth and throughput is driving the requirement for even faster clock frequencies. As valid signal windows shrink, signal integrity (SI) becomes a dominant factor in ensuring that memory interfaces perform flawlessly.
Chip and PCB-level design techniques can improve Simultaneous Switching Output (SSO) characteristics, making it easier to achieve the signal integrity required in wider memory interfaces. EDA vendors are making a wide range of tools available to designers for optimizing the signal integrity quality of memory interfaces. Features that are integrated on the FPGA silicon die, such as Digitally Controlled Impedance (DCI), simplify the PCB layout design and enhance performance. This article discusses these design techniques and hardware experiment results, illustrating the effect of design parameters on signal integrity.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- How to design 65nm FPGA DDR2 memory interfaces for signal integrity
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- Delivering High Quality Analog Video Signals With Optimized Video DACs
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY