How to design 65nm FPGA DDR2 memory interfaces for signal integrity
By David Banas, Xilinx
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- How to design secure SoCs Part IV: Runtime Integrity Protection
- Meeting signal integrity requirements in FPGAs with high-end memory interfaces
- Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension