Landscape for board design changes beyond 10G
Kinana Hussain, Vitesse
EETimes (5/7/2012 12:39 PM EDT)
The advent of 802.3ap Backplane Ethernet and its low-cost implementation at 10 Gbits/second, 10GBase-KR, has forever changed the way system designers think about the next generation of backplanes. While 10GBase-KR originally was promoted as a network-infrastructure backplane to migrate 10G networks to 40G and 100G Ethernet, it now finds greater utility as a backplane for servers and industrial platforms requiring multi-gigabit bandwidth. As systems demand interfaces capable of handling four-channel and 10-channel paths to 40/100G Ethernet, universal adoption of 10GBase-KR seems likely.
Although 10GBase-KR is a single-channel copper backplane operating at 10.3125 Gbits/s, the ease in implementing four channels has led some system vendors to look upon the single-channel backplane as the ideal stepping-stone for four-channel 40G Ethernet implementations. In the near future, experience gained in 10-Gbit multiple channels will allow 10-channel 100G Ethernet, supported by the current C form-factor pluggable (CFP) and extended-capability pluggable (CXP) modules. Eventually, the availability of faster chip-level transceivers and experience with faster board-level channels will allow four-channel 100G Ethernet, with each channel supporting up to 28 Gbits/s (25 Gbits plus forward error correction overhead). That standard will use the emerging CFP2 multisource agreement (CFP2 MSA) module.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related White Papers
- Embedded Virtualization Changes Comm Software Development Landscape
- The Complicated Chip Design Verification Landscape
- Shift Left for More Efficient Block Design and Chip Integration
- Rising respins and need for re-evaluation of chip design strategies
Latest White Papers
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant
- Attack on a PUF-based Secure Binary Neural Network
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics