Agile Verification for SoC Design
By Paul Cunningham, Cadence Design Systems
EETimes (June 3, 2021)
As agile methods are established to improve productivity and quality, interest is growing in hardware design.
Still, success in the hardware domain is generally perceived to have been limited. Reality is probably somewhat better than perception as some agility trends in hardware are not explicitly labeled as such.
For example, we see increasing efforts to decouple IP-level design and verification from SoC-level design and verification. In that case, each IP team runs asynchronously from SoC projects that operate on a “train model,” picking up whatever version of the IPs ready at the time an SoC design leaves the station.
While not branded as agile, this approach does align with an agile philosophy.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Early Interactive Short Isolation for Faster SoC Verification
- The SoC design: What’s next for NoCs?
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Creating core independent stimulus in a multi-core SoC verification environment
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design