Agile Verification for SoC Design
By Paul Cunningham, Cadence Design Systems
EETimes (June 3, 2021)
As agile methods are established to improve productivity and quality, interest is growing in hardware design.
Still, success in the hardware domain is generally perceived to have been limited. Reality is probably somewhat better than perception as some agility trends in hardware are not explicitly labeled as such.
For example, we see increasing efforts to decouple IP-level design and verification from SoC-level design and verification. In that case, each IP team runs asynchronously from SoC projects that operate on a “train model,” picking up whatever version of the IPs ready at the time an SoC design leaves the station.
While not branded as agile, this approach does align with an agile philosophy.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
Related White Papers
- Early Interactive Short Isolation for Faster SoC Verification
- The SoC design: What’s next for NoCs?
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Simplifying SoC Verification by communicating between HVL Env and processor
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models