HW/SW co-verification basics: Part 2 - Software-centric methods
Jason Andrews
EETimes (5/24/2011 2:22 AM EDT)
Most co-verification methods can be classified based on the execution engine used to run the hardware design. A secondary classification exists based on the method used to model the embedded system microprocessor. Generally, these methods fall into two categories, software centric and hardware centric. All have some pros and some cons. That is why there are so many of them, and it can be difficult to sort through the choices.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related White Papers
- HW/SW co-verification basics: Part 3 - Hardware-centric methods
- Transaction-based methodology supports HW/SW co-verification
- Approaches to accelerated HW/SW co-verification
- HW/SW co-verification basics: Part 1 - Determining what & how to verify
Latest White Papers
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant
- Attack on a PUF-based Secure Binary Neural Network
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics