Repeatable results with design preservation
By Kate Kelley, Xilinx
pldesignline.com (June 08, 2010)
Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores.
The complex modules newer designs, even when not changing, can present difficulties when attempting to meet quality-of-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.
The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations. This reduces the number of implementation iterations in the timing closure phase of the design.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- Preservation of Circuit Structure and Timing during Fault Emulation in FPGA
- PCI Express 3.0 needs reliable timing design
- PCI Express 3.0 needs reliable timing design
- Design patterns in SystemVerilog OOP for UVM verification
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension