PCI Express 3.0 needs reliable timing design

Amitava Banerjee & Jeetendra Ashok (Cypress)
EDN (October 14, 2018)

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard. Designers need to consider frequency, jitter, output standard, and other characteristics. With an understanding of the different PCIe architectures, their individual reference clock requirements, and how clock devices can help meet the various PCIe reference clock requirements, developers can design reliable systems.

PCIe Architecture

To understand how the reference clock architecture is used in PCIe, look at the typical clock architecture in an example application like Multi-Function Printers (MFP). The ASIC or SoC modules of MFPs have a built-in PCIe stack to simplify system design. A typical clocking interface of functional modules of an MFP is shown in Figure 1.

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