The evolution of design methodology
James Hogan
EETimes (11/24/2010 12:40 PM EST)
Editor's note: This is the first of a two part opinion piece authored by EDA luminaries Jim Hogan and Paul McLellan.Introduction
In nature, long periods of relatively stable environments are occasionally punctuated by large-scale changes that are the catalyst for evolution to create a large variety of mutations, and then for natural selection to weed out the unsuccessful ones.
The environment in which design methodology lives is also characterized by periods of relative stability punctuated by discontinuous change when the march of process nodes means that insignificant issues are suddenly major problems and when the scale of designs breaks the old methodologies. New approaches abound and, as in nature, the successful ones live on and others fall by the wayside.
Unlike in nature, however, these discontinuities are not rare and seem to come along roughly every ten years. We seem to be at another of these discontinuities today.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- The evolution of embedded devices: Addressing complex design challenges
- Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design
- Formal-based methodology cuts digital design IP verification time
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions