Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design
By Joe Sawicki, executive vice president of IC EDA division, Mentor
EETimes (June 19, 2019)
New design tools can develop circuits for AI and machine learning faster than ever. AI/ML is being used to make those same design tools even faster.
We are at the beginning of an age where artificial intelligence (AI) processing will advance in sophistication rapidly and become ubiquitous. While the concept of AI — giving machines the ability to mimic cognitive functions to learn and solve problems and then take an action — has been an academic discipline since the mid-1950s, it wasn’t until the last five years that AI processing, mostly in the form of machine learning (ML), could step out of the dimly-lit halls of research and supercomputer one-offs and move to practical everyday use. Why?
The amount of data generated from the internet and billions of smart devices alone has given us more than enough data to collect sizable data sets with which we can have ML filter and train ML-based systems to use. In addition, today we have enough ubiquitous high-performance compute power in smart devices and the high-bandwidth communications infrastructure to process and transfer massive data sets quickly. This compute power also gives us the canvas to develop ever more sophisticated and specialized algorithms for particular tasks, further expanding the application of AI/ML.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Articles
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
- Formal-based methodology cuts digital design IP verification time
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
Latest Articles
- FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant