Viewpoint: An Evolution in Design for Test
Sandeep Bhatia, Senior R&D Director, Oasys Design Systems
EETimes (2/16/2012 12:43 PM EST)
Designers relate to Design for Test (DFT) in much the way that small children relate to scary programs on TV: if they cover their eyes with their hands, perhaps it will go away. But every designer also knows that the design that they are so lovingly bringing into existence won’t see the light of day without addressing the test problem. After all, every single chip needs to be tested.
These days, there is a growing realization that DFT is evolving and, in particular, is not something that can be left to the end of the design cycle when some resident test expert lays his or her hands on the design and pronounces it good. We have all heard far too many stories of the last-minute chaos, and the inevitable schedule slips, that come from leaving test as an after thought. DFT in a modern design requires a systematic approach to planning early on.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- Moving DFT to RTL overcomes test vector issues
- The evolution of embedded devices: Addressing complex design challenges
- Pytest for Functional Test Automation with Python
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions