Design clock controllers for hierarchical test

Ron Press (Mentor Graphics)
EDN (July 18, 2014)

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation memory requirements, and put the ATPG process much earlier in the design cycle than other methods. In hierarchial test, users need to add scan wrappers to blocks so the blocks can be treated as independent plug-and-play blocks with plug-and-play patterns.

Wrapper insertion is a change to the typical scan insertion practices, but it is fully automated with modern DFT tools so the effort isn't very large. Often, most of the wrapper cells can simply reuse existing registered IO flops. The tools can automatically find the necessary cells for IO that aren't registered or you can set a threshold for when to add a new dedicated wrapper cell. The rest of the process is pretty simple, but the clocking used for hierarchical test needs to support plug-and-play pattern retargeting. Thus, OCC (on-chip clock controller) design and location is a very important consideration with hierarchical test.

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