Optimizing Automated Test Equipment for Quality and Complexity
By Jeorge Hurtarte, Teradyne (August 28, 2024)
AI is changing our world, driving unprecedented growth and innovation. High-performance chips at the heart of this revolution are marked by increasing complexity, precision requirements and integration of advanced technologies.
This explosive change is creating new demands on digital technology and the automated test systems on which semiconductor manufacturing relies. It is a comprehensive shift that demands flexible testing strategies to address new process architectures, heterogeneous packaging, and the complexities of hardware and software integration.
Today’s semiconductor test industry employs a multifaceted approach to tackle these diverse challenges. By advancing test equipment, integrating AI, adopting new standards, and optimizing test processes, the automated test equipment (ATE) industry is ensuring that it can keep pace with the rapid evolution of semiconductor technology and the needs of manufacturers.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- Shifting from functional to structured techniques improves test quality
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks