Optimizing Automated Test Equipment for Quality and Complexity
By Jeorge Hurtarte, Teradyne (August 28, 2024)
AI is changing our world, driving unprecedented growth and innovation. High-performance chips at the heart of this revolution are marked by increasing complexity, precision requirements and integration of advanced technologies.
This explosive change is creating new demands on digital technology and the automated test systems on which semiconductor manufacturing relies. It is a comprehensive shift that demands flexible testing strategies to address new process architectures, heterogeneous packaging, and the complexities of hardware and software integration.
Today’s semiconductor test industry employs a multifaceted approach to tackle these diverse challenges. By advancing test equipment, integrating AI, adopting new standards, and optimizing test processes, the automated test equipment (ATE) industry is ensuring that it can keep pace with the rapid evolution of semiconductor technology and the needs of manufacturers.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- SoC Test and Verification -> SoC complexity demands new test strategies
- Shifting from functional to structured techniques improves test quality
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models