Density Requirements at 28 nm
Joe Davis, Mentor Graphics
EETimes (3/12/2012 11:03 AM EDT)
In recent discussions with customers around the world, we have been hearing a surprising new message—that, at 28 nm, they have to care about density at the cell design level “like never before.” It’s surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly. However, where and how density is handled in the design process has evolved significantly along with the process technologies (Figure 1). In this article, I’ll take a look at how density has evolved from a back-end manufacturing issue that was of little interest to designers to a design concern that affects the layout of standard cell libraries.
To read the full article, click here
Related Semiconductor IP
- Hyper-Bandwidth Multichannel Memory Subsystem
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- Flash Memory LDPC Decoder IP Core
- HYPERBUS™ Memory Controller
- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
Related Articles
- Debunking myths about analog IP at 28 nm
- Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
- Mixed-Signal IP Design Challenges in 28 nm and Beyond
- DRC debugging challenges in AMS/custom designs at 20 nm
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor