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Compare 3,301 IP from 251 vendors (1 - 10)
  • General Memory Controller
    • The GMC (General Memory Controller) includes two memory controllers: The NOR/PSRAM memory controller, The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
  • Direct Memory Access Controller
    • Support up to 8 mem2mem channels with software configurable priority
    • Support up to 32 peripheral channels for pa-mem transfers
    • Support up to 16 (peripheral closely coupled) PER-type of memory-peripheral transfers
    • Support memory access with 1-16 beat(s) incrementing burst type
  • Flash Memory LDPC Decoder IP Core
    • Quasi cyclic (QC) – Algebraic constructed – LDPC Code 
    • Regular Parity Check Matrix 
    • Codeword length: 16 K 
    • Code rate 0.953 
    • No or very low error floor 
    • Parallel/Layered decoding 
  • Stream Direct Memory Access (SDMA)
    • The multi-channel Stream Direct Memory Access (SDMA) controller IP core provides high bandwidth direct memory access between memory and any IP peripherals with an AXI4-Stream interface for up to 16 channels.
    • The SDMA IP utilities a dedicated Write and Read circular buffer structure for data and descriptor(s) for each DMA channel, which helps in offloading data movement tasks from the Central Processing Unit (CPU) in processor-based systems.
    Block Diagram -- Stream Direct Memory Access (SDMA)
  • Deep Buffering Memory 1G Ethernet Switch
    • The 1G deep buffering memory Ethernet Switch is an advanced Ethernet switching IP that supports buffering large amounts of data in external RAM.
    • The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization, enabling per port and per queue shaping on egress ports.
    Block Diagram -- Deep Buffering Memory 1G Ethernet Switch
  • PSRAM Memory Controller IP
    • DFSPI – SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption) + … NOR & NAND Flash Memory Support
  • HYPERBUS™ Memory Controller
    • Support for HyperBus™ and xSPI standards
    • Bridges to APB, AHB, and AXI bus interfaces
    • Fully programmable SPI clock parameters
    • Automatic Slave Select control via SSCR register
    • Technology-independent HDL design
  • High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
    • The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin.
    • The HBM3 IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
    Block Diagram -- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
  • NAND Memory Controller
    • The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode.
    • This core also supports error correction on the fly without any processor intervention. Up to 8 memory chips can be accessed on the same bus with write speed of 100Mbps and read speeds of 120Mbps.
  • High-Performance Memory Controller II SDRAM Intel® FPGA IP Core
    • The High-Performance Memory Controller II SDRAM Intel FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 MHz
    • The intellectual property (IP) core initializes the memory devices, manages SDRAM banks, translates read-and-write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.
    Block Diagram -- High-Performance Memory Controller II SDRAM Intel® FPGA IP Core
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