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Compare 3,178 IP from 255 vendors (1 - 10)
  • sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
    • Foundry sponsored - sROMet compiler - TSMC 55 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
  • Fault Tolerant DDR2/DDR3/DDR4 Memory controller
    • FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
    • It uses a strong error correction code to achieve exceptional fault tolerance
    Block Diagram -- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
  • Memory Compilers
    • Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.
  • DDR4 IO for memory PHY, 3200Mbps on SMIC 40nm
    • The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
    • The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM.
  • PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
    • The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device
    • The TX is designed to send information from PHY to PSRAM and RX is designed to receive information which is from PSRAM
    • there are bi-direction DQ IO, TX-only CK IO, filler cell with differrent size and VDDQ/VSS power clamp IO included in the PHYIOs.
  • DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
    • The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
    • The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM._x000D_ It supports DDR5&DDR4 interface
    • The DDR5 DQ data rate can be up to 4800Mb/s, and the DDR4 DQ data rate can be up to 3200Mb/s and CA is SDR mode.
  • DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
    • The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
    • The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM.
  • General Memory Controller
    • The GMC (General Memory Controller) includes two memory controllers: The NOR/PSRAM memory controller, The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
  • Direct Memory Access Controller
    • Support up to 8 mem2mem channels with software configurable priority
    • Support up to 32 peripheral channels for pa-mem transfers
    • Support up to 16 (peripheral closely coupled) PER-type of memory-peripheral transfers
    • Support memory access with 1-16 beat(s) incrementing burst type
  • Flash Memory LDPC Decoder IP Core
    • Quasi cyclic (QC) – Algebraic constructed – LDPC Code 
    • Regular Parity Check Matrix 
    • Codeword length: 16 K 
    • Code rate 0.953 
    • No or very low error floor 
    • Parallel/Layered decoding 
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Semiconductor IP