Compiling FPGA netlists for formal verification
Joachim Pistorius and K. Chandrashekar, Altera Corp.
02/06/2006 9:00 AM EST, EE Times
Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL description into a bitstream format that can program the FPGA is increasingly complicated. This in turn increases the demand for verifying the design transformations.
Even though FPGAs are reprogrammable, an error detected late in the design cycle, or even after the board has gone into production, can still be very expensive. In addition, some FPGA vendors offer migration to structured ASICs, in which a fabricated design cannot be reprogrammed. Therefore, it is even more important for designs targeted towards structured ASIC device families that implementation errors are caught early in the development phase.
For all of the above reasons, customers want to verify the functional correctness of the RTL-to-bitstream design transformations. Formal methods are becoming increasingly popular in the FPGA design methodology, as they offer several advantages over the traditional method of vector-based simulation. Some of these advantages are shorter runtime, better functional coverage, and no need for test vectors.
02/06/2006 9:00 AM EST, EE Times
Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL description into a bitstream format that can program the FPGA is increasingly complicated. This in turn increases the demand for verifying the design transformations.
Even though FPGAs are reprogrammable, an error detected late in the design cycle, or even after the board has gone into production, can still be very expensive. In addition, some FPGA vendors offer migration to structured ASICs, in which a fabricated design cannot be reprogrammed. Therefore, it is even more important for designs targeted towards structured ASIC device families that implementation errors are caught early in the development phase.
For all of the above reasons, customers want to verify the functional correctness of the RTL-to-bitstream design transformations. Formal methods are becoming increasingly popular in the FPGA design methodology, as they offer several advantages over the traditional method of vector-based simulation. Some of these advantages are shorter runtime, better functional coverage, and no need for test vectors.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- How formal verification saves time in digital IP design
- Don't over-constrain in formal property verification (FPV) flows
- Formal Verification Has It Covered!
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS