Challenges in LBIST validation for high reliability SoCs
Abhinav Gaur & Gaurav Jain (Freescale)
EDN -- July 19, 2014
Logic built-in self test (LBIST) is being used in SoCs for increasing safety and to provide a self-testing capability. LBIST design works on the principle of STUMPS architecture. STUMPS is a nested acronym, standing for Self-Test Using MISR (Multiple Input Signature Register) and Parallel SRSG (Shift Register Sequence Generator). It consists of a Pseudo Random pattern generator (PRPG) for generating the test stimuli for the scan input, and Multiple Input Signature Register (or MISR) for collecting the scan output. If the final MISR signature matches with the golden or expected MISR signature, the LBIST status is “Pass”.
For any SoC that provides the LBIST functionality, there will be a need for tester patterns for production, for checking whether the LBIST is working properly on each of the samples being delivered to the customer. This paper will discuss the various challenges while developing these LBIST tester patterns for production, and ways of creating such patterns efficiently.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Reliability challenges in 3D IC semiconductor design
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions