40G UCIe IP Advantages for AI Applications
By Aparna Tarde, Sr. Technical Product Manager and Manuel Mota, Sr. Product Manager - Synopsys
The deployment of generative AI in the devices we use every day is growing, driving demand for large language model sizes and higher compute performance. According to a presentation by Yole Group at the 2024 OCP Regional Summit, ‘For training on GPT-3 with 175 billion parameters, we estimate that between 6,000 and 8,000 A100 GPUs would have required up to a month to complete.’ Growing HPC and AI compute performance requirements are driving the deployment of multi-die designs, integrating multiple heterogeneous or homogenous dies in a single standard or advanced package. For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.
To read the full article, click here
Related Semiconductor IP
- UCIe RX Interface
- AXI-S Protocol Layer for UCIe
- UCIe PHY (Die-to-Die) IP
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- UCIe D2D Adapter
Related Articles
- 40G UCIe IP Advantages for AI Applications
- Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
- Boosting RISC-V SoC performance for AI and ML applications
- Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability