Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
By Danial Noori Zadeh and Mohamed B. Elamien, McMaster University, Canada
Electronic Design Automation (EDA) in analog Integrated Circuits (ICs) has been the focus of extensive research; however, unlike its digital counterpart, it has not achieved widespread adoption. In this systematic review, we discuss recent contributions in the last five years, highlighting methods that address data scarcity, topology exploration, process-voltage-temperature (PVT) variations, and layout parasitics. Our goal is to support researchers new to this domain by creating a comprehensive collection of references and practical application guidelines. We provide a methodological review of state-of-the-art machine learning (ML) approaches, including graph neural networks (GNNs), large language models (LLMs), and variational autoencoders (VAEs), which have been successfully applied to analog circuit sizing tasks. To the best of authors’ knowledge, this is the first review to comprehensively explore the application of generative AI models in analog IC circuit design. We conclude that future research could focus on few-shot learning with domain-adaptation training of generative AI methods to simplify the design tasks such as human-tool interaction or guided design space exploration.
To read the full article, click here
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related Articles
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability