Reclaiming lost yield through methodical power integrity optimization
Christian Petersen, Teklatech A/S
EETimes (4/1/2013 10:32 AM EDT)
As designs are moving to 28nm and beyond, designers fully experience the effects of the much higher power density and diminishing effectiveness of decoupling capacitances at these geometries: failures due to dynamic power noise integrity issues is a significant contributor to yield loss in many designs. Synchronous switching and increasing di/dt at advanced process nodes (Figure 1) makes it increasingly challenging for designers to deal with on-chip dynamic voltage drop (DVD) and high frequency electromagnetic interference (EMI). And neither is to be taken lightly; studies have shown DVD fluctuations introduce sizable gate delays causing timing-related yield loss, and EMI from digital switching similarly cause mixed-signal yield loss due to compromised noise integrity.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related White Papers
- Making ESL power optimization a reality
- Leakage power optimization for 28nm and beyond
- Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
- Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"