Understanding DDR SDRAM timing parameters
Deepak Kumar, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
EETimes (6/25/2012 3:05 PM EDT)
Many engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM.
To begin with, let's first understand how different DDRs are rated or classified. If we want to buy a DDR module from market, we have to consider many parameters like size, speed, timing specs, brand etc. So, we have many options to choose from. To have a better understanding of these ratings, let’s see how these are presented to the buyers.
To read the full article, click here
Related Semiconductor IP
- SDRAM DDR Controller
- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
- DDR SDRAM Controller - Non-Pipelined
- DDR SDRAM Controller - Pipelined
- AMBA AHB Bus to DDR SDRAM Controller
Related Articles
- The Love/Hate Relationship with DDR SDRAM Controllers
- DDR SDRAM Controller IP Designed for Reuse
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems
Latest Articles
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices
- Toki: Profiling HBM Performance on FPGA Systems with RISC-V Soft Cores and PCIe Host DMA Traffic
- VSpector: Specification-Driven Bug Detection for RISC-V CPUs