DDR SDRAM Controller

Key Features

• Supports industry standard Double Data Rate (DDR) SDRAM from 64Mbit to 512Mbit device sizes.
• Page hit detection to support multiple column accesses within the same row.
• Pipeline access allows continuous data bursting.
• External pin reduction by transferring 2 bits of data per pin.
• Provide user data at twice the data width compared to DDR SDRAM data.
• Programmable SDRAM data width and user word size.
• Supports burst lengths of 2, 4 and 8 words.
• Programmable SDRAM access timing parameters.
• Supports multiple external SDRAM banks.
• Automatic refresh generation with programmable refresh intervals.
• Self-refresh mode to reduce system power consumption.
• Programmable memory configuration registers.
• Integrated data buffer synchronizes user interface with DDR SDRAM data.
• Designed with synthesizable HDL for ASIC and FPGA synthesis.

Block Diagram

Deliverables

• netlist
• routing control file
• verilog/vhdl source code
• test vectors
• test benches
• design templates.

Technical Specifications