An RTL to GDSII approach for low power design: A design for power methodology
Aveek Sarkar, Apache Design Solutions Inc.
EETimes (1/12/2011 8:12 AM EST)
The statistics on infrastructure and computing needs for the Internet are sobering. The volume of data that is uploaded onto YouTube every minute of the day exceeds 35 hours of video. Facebook, if it were a nation, would be the third most populous after China and India. Amazon.com withstands onslaughts from hordes of Black Friday online shoppers by having a massive compute infrastructure that sells practically everything. All these services are enabled through the creation and maintenance of large data centers that cater to the increasing amount of content and traffic on the Internet that is driven by the proliferation of broadband and mobile handset connectivity. If you consider the Power Usage Effectiveness (PUE) metric used to judge the efficiency of servers and cooling systems, the current ratio prevalent in the industry is 1.9, this means that almost half the power in a data center is used to cool servers with only the remaining half available for the computations themselves [1].
As the compute power of handheld devices approaches that of traditional computers through the use of GHz+ processor cores and increased levels of functionality, the power signature of such devices must be carefully controlled to not only make the products commercially viable, but to make them competitive in the market. As seen in figure 1, if the power density of a handheld device exceeds a narrow band, it will be too hot and must be re-designed because a human hand will not be able to hold the device for any period of time.
To read the full article, click here
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- An ESD efficient, Generic Low Power Wake up methodology in an SOC
- Low Power Design in SoC Using Arm IP
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
Latest White Papers
- Boosting RISC-V SoC performance for AI and ML applications
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU