How to simplify power design development and evaluation for FPGA-based systems

Power consumption in electronic devices and the design of power systems is an increasingly complex task. Static current levels coupled with increased dynamic current demands imply greater IR drops in power distribution systems. Operating temperature requirements require sophisticated heat sink and airflow measurements. The Virtex-5 FPGA System Monitor features on-die temperature and voltage measurement capabilities that provide valuable information for the development, evaluation, debugging, optimization, and qualification of PCB power designs. This article explains how to configure System Monitor's external channels for power monitoring and provides PCB implementation recommendations/guidelines.

System Monitor Overview

The Virtex-5 FPGA System Monitor has, as its core, a 200 kilo-Samples-Per-Second (kSPS) Analog-to-Digital Converter (ADC). Fig 1 shows a block diagram of the System Monitor.

1. The System Monitor Block.
(Click this image to view a larger, more detailed version)

The System Monitor allows unprecedented and convenient access to vital on-chip analog FPGA information. The inputs to the ADC are on-die temperature and voltage sensors. Using its 17 available external channels, the System Monitor provides for the measurement of the physical environment of the PCB or enclosure. The control logic implements common monitoring features, including automatic channel sequencing, filtering, and alarms. All of these features are user programmable and can be customized at run time through the register file interface accessible in the FPGA logic through the Dynamic Reconfiguration Port (DRP). The DRP is a standard bus interface available in many Xilinx FPGA blocks. This port enables updating the configuration of a particular block in a dynamic manner. Alternatively, the register file interface is accessed externally through the JTAG Test Access Port (TAP). Indeed, access to the System Monitor feature is available even before the device is configured using the JTAG TAP.

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